Altera Cyclone III FPGA入门开发方案

      Altera公司的Cyclone III FPGA系列是成本优化而存储器容量大的FPGA,具有低功耗高集成度,从而降低了成本.

       广泛应用在汽车电子,消费类产品,各种尺寸的显示器,工业领域,视频和图像处理以及无线通信和军用.本文介绍了Cyclone III FPGA系列的主要性能,以及Cyclone III格FPGA的入门套件主要性能,开发板的电路图以及所有的元器件清单(BOM).

      The Cyclone® III FPGA family offered by Altera is a cost-optimized, memory-rich FPGA family. Cyclone III FPGAs are built on TSMCs 65-nm low-power (LP) process technology with additional silicon optimizations and software features to minimize power consumption. With this third generation in the Cyclone series, Altera broadens the number of high volume, cost-sensitive applications that can benefit from FPGAs.

      Cyclone III devices are designed to offer low-power consumption and increased system integration at reduced cost.

      Reduced Cost
      Cyclone III devices deliver the lowest device and system costs       based on the following facts:

      ■ Staggered I/O ring to lower die area
      ■ Wide range of low cost packages
      ■ Support for low-cost serial flash and commodity parallel flash devices for configuration

      Lowest-Power 65-nm FPGA

      Cyclone III devices are the lowest-power 65-nm FPGAs designed via TSMC’s 65-nm low power process and Altera’s power aware design flow. Cyclone III devices support hot-socketing operation;therefore, unused I/O banks can be powered down when the devices to which they are connected are turned off. 

      Benefits of the Cyclone III devices low-power operation include:

      ■ Extended battery life for portable and handheld applications
      ■ Enabled operation in thermally challenged environments
      ■ Eliminated or reduced cooling system costs
Increased System Integration
Cyclone III devices provide increased system integration by offering the following features:
      ■ Density is up to 119,088 logic elements (LEs) and memory is up to 3.8 Mbits.
      ■ High memory to logic ratio for embedded DSP applications
      ■ Highest multiplier-to-logic ratio in the industry at every density; 260 MHz multiplier performance
      ■ High I/O count, low- and mid-range density devices for user I/O constrained applications
     ■ Up to four phase-locked loops (PLLs) provide robust clock management and synthesis for device clocks, external system clocks, and I/O interfaces
Up to five outputs per PLL
     Cascadable to save I/Os, ease PCB routing, and reduce the number of external reference clocks needed
Dynamically reconfigurable to change phase shift, frequency multiplication/division, and input frequency in-system without reconfiguring the device
    ■ Support for high-speed external memory interfaces including DDR, DDR2, SDR SDRAM, and QDRII SRAM at up to 400 Mbps
Auto-calibrating physical layer (PHY) feature accelerates timing closure process and eliminates variations over process, voltage and temperature (PVT) for DDR, DDR2, SDRAM, and QDRII SRAM interfaces
    ■ Up to 534 user I/O pins arranged in 8 I/O banks that support a wide range of industry I/O standards
Up to 875 Mbps receive and 840 Mbps transmit LVDS communications
LVDS, RSDS®, mini-LVDS and PPDS® transmission without the use of external resistors
Supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS, RSDS, and PPDS; PCI Express and Serial Rapid I/O are supported using external PHY devices
       ■ Multi-value on-chip termination (OCT) support with calibration feature to eliminate variations over PVT
       ■ Adjustable I/O slew rates to improve signal integrity
       ■ Support for low-cost Altera® serial flash and commodity parallel flash configuration devices from Intel
       ■ Remote system upgrade feature without requiring an external controller
       ■ Dedicated Cyclic Redundancy Code (CRC) checker circuitry to detect single event upset (SEU) conditions
       ■ Nios® II embedded processors for Cyclone III devices offer low cost and custom-fit embedded processing solutions
       ■ Broad portfolio of pre-built and verified intellectual property cores from Altera and Altera Megafunction Partners Program (AMPPSM) partners

                         图1. Cyclone® III FPGA方框图.

      Cyclone® III入门套件:

       The Cyclone® III starter board provides a hardware platform that offers a unique opportunity to customize your development environment via expansion connectors and daughter cards as well as evaluate the featurerich, low-power Altera® Cyclone III device. For more functionality, the starter board can be expanded through daughter cards connected to the Altera High Speed Mezzanine Card (HSMC) connector. Altera and development kit partners are creating HSMC daughter cards that allow you to expand the functionality of the board.

       The main features of the Cyclone III starter board are:
       ■ Low-power consumption Altera Cyclone III EP3C25 chip in a 324-pin FineLine BGA (FBGA) package
       ■ Expandable through HSMC connector
       ■ 32-Mbyte DDR SDRAM
       ■ 16-Mbyte parallel flash device for configuration and        storage
       ■ 1 Mbyte high-speed SSRAM memory
       ■ Four user push-button switches
       ■ Four user LEDs
The main advantages of the Cyclone III starter board are:
       ■ Facilitates a fast and successful FPGA design experience with helpful example designs and demonstrations.
       ■ Directly configure and communicate with the Cyclone III device via the on-board USB-Blaster; circuitry and JTAG header
       ■ Active Parallel flash configuration
       ■ Low power consumption
       ■ Cost-effective modular design
开发板的元器件:
       ■ Altera Cyclone III EP3C25F324 FPGA
25K logic elements (LEs)
66 M9K memory blocks (0.6 Mbits)
16 18x18 multiplier blocks
Four PLLs
214 I/Os
Clock management system
One 50 MHz clock oscillator to support a variety of protocols
The Cyclone III device distributes the following clocks from its on-board PLLs:
DDR clock
SSRAM clock
Flash clock
HSMC connector
Provides 12 V and 3.3 V interface for installed daughter cards
Provides up to 84 I/O pins for communicating with HSMC daughter cards
General user-interface
Four user LEDs
Two board-specific LEDs
Push-buttons:
System reset
User reset
Four general user push-buttons
Memory subsystem
Synchronous SRAM device
1-Mbyte standard synchronous SRAM
167-MHz
Shares bus with parallel flash device
Parallel flash device
16-Mbyte device for active parallel configuration and storage
Shares bus with SRAM device
DDR SDRAM device
56-pin, 32-Mbyte DDR SDRAM
167-MHz
Connected to FPGA via dedicated 16-bit bus
Built-in USB-Blaster interface
Using the Altera EPM3128A CPLD
For external configuration of Cyclone III device
For system debugging using the SignalTap® and Nios® debugging console
Communications port for Board Diagnostic graphical user interface (GUI)

图2.开发板的方框图.

                          图3. Cyclone III FPGA开发板外形图.

      Cyclone III FPGA Datasheet请见

      Cyclone III FPGA开发板详细电路图见(pdf):

       点此查看全文

本文来源：Altera公司    作者：Altera公司

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