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TI DM355网络监视照相机解决方案

2008-01-04 嵌入式在线收藏 | 打印

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications.

Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance, high quality, low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module

Data and program Memory Management Units (MMUs) with table look-aside buffers.

Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

DM355 performance is enhanced by its MPEG/JPEG co-processor. The MPEG/JPEG co-processor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE)

A Video Processing Back-End (VPBE)
The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

       An inter-integrated circuit (I2C) Bus interface
       Two audio serial ports (ASP)
       Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
       A 64-bit watchdog timer
       Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals

       Three UARTs with hardware handshaking support on one UART
       Three serial port Interfaces (SPI)
       Four pulse width modulator (PWM) peripherals
       Four real time out (RTO) outputs
       Two Multi-Media Card / Secure Digital (MMC/SD) interfaces
       A USB 2.0 full and high-speed device and host interface
       Two external memory interfaces:
       An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
       A high speed synchronous memory interface for DDR2/mDDR.

Features

       High-Performance Digital Media System-on-Chip
       216- and 270-MHz ARM926EJ-S Clock Rate
       Fully Software-Compatible With ARM9
       ARM926EJ-S Core
       Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
       DSP Instruction Extensions and Single Cycle MAC
       ARM Jazelle Technology
       EmbeddedICE-RT Logic for Real-Time Debug
       ARM9 Memory Architecture
       16K-Byte Instruction Cache
       8K-Byte Data Cache
       32K-Byte RAM
       8K-Byte ROM
       Little Endian
       Video Processing Subsystem
       Front End Provides:
       Hardware IPIPE for Real-Time Image Processing
       CCD and CMOS Imager Interface
       14-Bit Parallel AFE (Analog Front End) Interface Up to 75 MHz
       Glueless Interface to Common Video Decoders
       BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
       Histogram Module
       Resize Engine
       Resize Images From 1/16x to 8x
       Separate Horizontal/Vertical Control
       Two Simultaneous Output Paths
       Back End Provides:
       Hardware On-Screen Display (OSD)
       Composite NTSC/PAL video encoder output
       8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
       BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
       Supports digital HDTV (720p/1080i) output for connection to external encoder

       External Memory Interfaces (EMIFs)
       DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
       Asynchronous16-/8-bit Wide EMIF (AEMIF)
       Flash Memory Interfaces
       NAND (8-/16-bit Wide Data)
       OneNAND(16-bit Wide Data)
       Flash Card Interfaces
       Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
SmartMedia
       Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
       USB Port with Integrated 2.0 High-Speed PHY that Supports
       USB 2.0 Full and High-Speed Device
       USB 2.0 Low, Full, and High-Speed Host
       Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
       One 64-Bit Watch Dog Timer
       Three UARTs (One fast UART with RTS and CTS Flow Control)
       Three Serial Port Interfaces (SPI) each with two Chip-Selects
       One Master/Slave Inter-Integrated Circuit (I2C) Bus™
       Two Audio Serial Port (ASP)
       I2S and TDM I2S
       AC97 Audio Codec Interface
       S/PDIF via Software
       Standard Voice Codec Interface (AIC12)
       SPI Protocol (Master Mode Only)
       Four Pulse Width Modulator (PWM) Outputs
       Four RTO (Real Time Out) Outputs
       Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
       On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
       Configurable Power-Saving Modes
       Crystal or External Clock Input (typically 24 MHz or 36 MHz)
       Flexible PLL Clock Generators
       Debug Interface Support
       IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
       ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
       Device Revision ID Readable by ARM
       337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
       90nm Process Technology
       3.3-V and 1.8-V I/O, 1.3-V Internal

       DaVinci imaging-processing pipeline.

       SYSTEM BLOCK DIAGRAMS

       Camera: Surveillance Mid End Networked

Camera: Surveillance Mid End Networked

       The change from traditional Analog Surveillance Cameras to IP Surveillance Cameras is driven by the flexibility to use the latest software to compress and analyze the video stream. Today video CODECs (H.264, MPEG4 etc.) are typically used to compress images with CIF (352 x 288) resolution at 25fps with a trend towards higher resolutions. Higher resolution images allow for the implementation of features like virtual PTZ eliminating the need for electrical motors to move the camera and operate the zoom lens. The results are smaller cameras with lower power consumption.

       SYSTEM BLOCK DIAGRAMS
       Camera: Surveillance Low End Networked

SYSTEM BLOCK DIAGRAMS
Cell Phone

       CODECs

       Voice-Band Codecs

       DC/DC Converters (Integrated Switch)

       Inductorless DC/DC Regulators (Charge Pumps)

       DC/DC Converters (Integrated Switch)

       Single Channel LDO

       High Speed Amplifiers (Greater than equal to 50MHz)

       Operational Amplifiers

       DC/DC Converters (Integrated Switch)

       Inductorless DC/DC Regulators (Charge Pumps)
A modern cell phone provides 2-way communications using one of several cellular standards (GSM, CDMA, TDMA, AMPs, etc.). It often integrates one of more of the following functions:
       vibrating ringer
       polyphonic ringer
       touch-screen
       still and/or video camera
       broadcast radio receiver (FM, AM)
       MP3 player
       PC connection

       SYSTEM BLOCK DIAGRAMS
Wireless Infrastructure: TD-SCDMA RX/TX